Machine Learning Engineer (ML for EDA & Agentic AI)

Company Type: Venture-Backed Agentic AI Startup ($134M Funding)Location: San Jose, CACompensation: $180,000 – $350,000+ base salary + Generous Equity Work Setup & Logistics: • Work Arrangement: 5 days in-office in San Jose, CA (On-site). • Visa & Citizenship Status: Open to H-1B transfers and simple visa transfers (General new visa sponsorships are not offered; U.S. Citizens, Green Card holders, and H-1B transfers eligible). • Relocation Assistance: Relocation support is available. Role Overview:Join a pioneer in agentic AI for semiconductor design to improve the frontier models powering automated chip design and verification. Working alongside world-renowned AI researchers and EDA industry veterans, you will take cutting-edge LLM post-training experiments directly into production for top global semiconductor enterprise clients. Overall Day-to-Day Responsibilities: • Model Training & Fine-Tuning: Train, fine-tune, and post-train LLMs for hardware design, RTL code generation, and verification tasks using Supervised Fine-Tuning (SFT) and Reinforcement Learning (RLHF). • Data Pipelines & Benchmarks: Build robust training data pipelines, synthetic data generation scripts, and domain-specific evaluation harnesses to test agent accuracy and reliability. • Production Deployment: Collaborate with systems engineers and research scientists to optimize model latency, batching strategies, and inference workloads. • Research to Product: Experiment with emerging LLM architectures and open-source models, applying promising research to real-world engineering workflows. Highlighted Skills & Requirements: • 3–10 years of experience as an ML Engineer or a recent PhD with a research focus in AI/ML. • Hands-on expertise training or fine-tuning LLMs (SFT, RLHF, post-training methods) using Python and PyTorch. • Solid understanding of modern LLM architectures, transformer models (Hugging Face), and evaluation harnesses. • Nice to Have: Proficiency in C++, CUDA, high-performance inference frameworks (vLLM, SGLang, Ray), or familiarity with hardware design languages (Verilog, SystemVerilog, RTL) and EDA tools. Educational Background: • B.S., M.S., or Ph.D. in Computer Science, Electrical Engineering, Computer Engineering, or a related quantitative field. "Synopsys Inc" OR "Cadence" OR "Siemens" OR "Keysight Technologies" OR "NVIDIA" OR "Google" OR "Apple" OR "Marvell Technology" OR "Samsung Electronics" OR "AMD"